RISC-V ISA begins at IIT Madras

NEW DELHI, JULY 18: The Indian Institute of Technology Madras is hosting RISC-V Workshop, a free and open Instruction Set Architecture (ISA) that enables a new era of processor innovation through open standard collaboration.

Born in academia and research, RISC-V ISA aims to deliver a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The conference is organized by RISC-V Foundation, which was founded in 2015 with IIT Madras being one of the Founder Members. It comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward.

Speaking about the importance of this event, Workshop Vice-Chair Prof. Kamakoti Veezhinathan, Computer Science and Engineering Department, IIT Madras, said, “The National Microprocessor Development Program, funded by Ministry of Electronics and Information Technology, Government of India, aims to develop indigenous microprocessor for the country. The processor code being developed as part of this program is based on RISC-V ISA.”

The RISC-V Foundation has a Board of Directors comprising seven representatives from Bluespec, Inc.; Google; Microsemi; NVIDIA; NXP; University of California, Berkeley; and Western Digital.

Prof Kamakoti said that Open Source Architecture was important with the advent of digital world. Different organizations required different types of processing elements and different computing powers. These should be quickly configurable to suit the individual companies or country’s requirements.

Further, Prof. Kamakoti added, “These companies and countries need a good software support for the hardware they develop. In this context, an Open Source Extensible Instruction Set Architecture (ISA) is of utmost necessity. The RISC V is an open source ISA promoted by RISC V Foundation, for which IIT Madras is one of the early founding members.”