IIT Madras starts registrations for symposium on ‘Future of India’s Electronics and Computers’

The 1-day event is scheduled on August 6, 2023 at the IIT Madras Research Park in Taramani, Chennai.

IIT Madras starts registrations for symposium on ‘Future of India’s Electronics and Computers’ IIT Madras starts registrations for symposium on ‘Future of India’s Electronics and Computers’ (Image Source: Careers360)
Tanuja Joshi | Aug 1, 2023 - 4:43 p.m. IST
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NEW DELHI: Indian Institute of Technology (IIT) Madras and IIT-M Pravartak Technologies Foundation have jointly opened the registrations for the ‘Digital India RISC-V’ symposium. The one-day event on 'The future of Electronics in India through the RISC-V pathway,' is scheduled on August 6, 2023 at the IIT Madras Research Park in Taramani, Chennai.

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Registration for the symposium is open to all and is free of cost with a limited number of seats available. Interested participants can register themselves on the official website of symposium at pravartak.org.in/dirv_tech_confluence_registration.

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The symposium aims to bring together students, industry professionals, and researchers interested in Reduced Instruction Set Computer (RISC) V designs. Participants at the event will gain insights into the expanding RISC-V ecosystem in India and explore the latest developments and trends in the field of processor design and innovation through open standard collaboration.

The event will be attended by Rajeev Chandrasekhar, the Minister of State in the Ministries of Electronics and Information Technology, and Skill Development and Entrepreneurship, Government of India along with V Kamakoti, the director of IIT Madras, who played a key role in developing 'SHAKTI,' India’s first indigenously-designed microprocessor based on RISC-V Instruction Set Architecture (ISA).

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Attendees will be able to explore interactive stalls showcasing indigenous RISC-V processors, take part in an engaging hackathon conclusion, and attend a special investor session.

The Reduced Instruction Set Computer (RISC) is different from the prevalent 'CISC' (Complex Instruction Set Computer) architecture. The 'V' in RISC-V represents the fifth generation. The RISC-V project's origins can be traced back to 2010, and its ISA has been instrumental in enabling a new era of processor innovation through open standard collaboration. RISC-V ISA is dedicated to delivering a new level of free, extensible software and hardware freedom in computer architecture, thereby paving the way for the next 50 years of computing design and innovation.

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IIT Madras, one of the founder members of the RISC-V Foundation established in 2015. The symposium coincides with the ongoing DIR-V (Digital India RISC-V) microprocessor programme, initiated in 2022 by the Government of India, with the ambitious goal of enabling the creation of future-ready microprocessors in India, for the global market, and achieving industry-grade silicon and Design wins by December 2023.


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