IIT Bombay research team wins VLSI user design competition
Sheena Sachdeva | April 15, 2025 | 06:59 PM IST | 1 min read
IIT Bombay research team and Semiconductor Laboratory jointly developed a semiconductor that aims to secure ‘electronic systems against unauthorised access.’
NEW DELHI: A research team from Indian Institute of Technology (IIT) Bombay has won the VLSI User Design Track competition at 38th International Conference on VLSI Design and 24th International Conference on Embedded Systems. The event was held in Bengaluru from January 4-8, 2025.
The winning design features patented PECVD SiO2 capacitors as anti-fuse elements with low programming voltage (3.3V) and CMOS integration at 180nm node. The innovation aims to address the need to secure electronic systems against unauthorised access.
The chip was designed at IIT Bombay and fabricated at the Semiconductor Laboratory (SCL), Chandigarh, by adopting a One Time Programmable (OTP) memory technology. “This is evidence of India’s homegrown innovation in semiconductor design and manufacturing,” an IIT Bombay statement said.
IIT Bombay: VLSI user design
Speaking on the success of the team, Uadayan Ganguly, professor of electrical engineering, IIT Bombay, said, “As India builds fab with imported technology, the ability to build indigenous memory technology at scale is essential for sustenance and growth of the semiconductor ecosystem. Our capability is a key enabler for the same.”
“This OTP technology will enable indigenously designed and manufactured security chips essential for data protection and secure communication. It has particular promise for applications requiring radiation-hardened memory suitable for space missions and critical areas like e-passports and driving licences,” IIT Bombay said in a statement.
The design technology will be developed by the IIT Bombay team and soon will be commercialised through NumeloTech, an incubated startup under the Society of Innovation and Entrepreneurship (SINE) at the institute.
The IIT Bombay research team comprised former senior project research scientist Ajay Kumar Singh, project research scientist Shreeniwas Daultabad, senior project research scientist Shatadal Chatterjee; and two PhD students/research scholars Abhishek Kadam and Shreyas Deshmukh, developed the design.
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